The present invention relates to a semiconductor integrated circuit having a voltage limiter circuit provided in a semiconductor chip.
The recent advances made in the area of high integration of semiconductor integrated circuits have been significant. As an example, an MOS dynamic memory (hereinafter referred to as DRAM) is now mass-produced for 4 megabits and, experimentally, has been shown to be manufacturable, for 16 megabits. Such high integration and large capacity bring about increased power consumption due to increased parasitic capacitances. Further, the high integration and the large capacity are mainly supported by scaling-down of elements but the scaling-down of the elements reduces the breakdown immunity of the elements. In recent years, accordingly, there has developed a tendency towards reducing an operating voltage of circuits within the semiconductor integrated circuit device from the standpoint of desiring both a of reduction of the power consumption and securement of the breakdown immunity of the elements.
In one method of reducing the operating voltage of the circuit, a voltage limiter circuit is provided in a semiconductor integrated circuit chip to reduce a supply voltage (internal supply voltage) within the chip. In this method, a supply voltage (external supply voltage) applied to the chip may be the same as a supply voltage generally used and, accordingly, a user can conveniently use it.
The voltage limiter circuits of this type are disclosed in JP-A-2-198096 and JP-A-1-136361 and IEEE Journal of Solid State Circuits, Vol. SC-22, No. 3, pp. 437-441, June 1987. Any one of these voltage limiter circuits can be provided within a chip to lower an external supply voltage applied to the chip to form an internal supply voltage which is supplied to a memory circuit or a logic circuit provided in the same chip.